PCLK_TIMER3=CCLK_DIV_4, PCLK_SYSCON=CCLK_DIV_4, PCLK_I2S=CCLK_DIV_4, PCLK_UART2=CCLK_DIV_4, PCLK_TIMER2=CCLK_DIV_4, PCLK_GPIOINT=CCLK_DIV_4, PCLK_RIT=CCLK_DIV_4, PCLK_I2C2=CCLK_DIV_4, PCLK_SSP0=CCLK_DIV_4, PCLK_PCB=CCLK_DIV_4, PCLK_MC=CCLK_DIV_4, PCLK_QEI=CCLK_DIV_4, PCLK_UART3=CCLK_DIV_4, PCLK_I2C1=CCLK_DIV_4
Peripheral Clock Selection register 1.
| PCLK_QEI | Peripheral clock selection for the Quadrature Encoder Interface. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| PCLK_GPIOINT | Peripheral clock selection for GPIO interrupts. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| PCLK_PCB | Peripheral clock selection for the Pin Connect block. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| PCLK_I2C1 | Peripheral clock selection for I2C1. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| RESERVED | Reserved. |
| PCLK_SSP0 | Peripheral clock selection for SSP0. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| PCLK_TIMER2 | Peripheral clock selection for TIMER2. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| PCLK_TIMER3 | Peripheral clock selection for TIMER3. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| PCLK_UART2 | Peripheral clock selection for UART2. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| PCLK_UART3 | Peripheral clock selection for UART3. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| PCLK_I2C2 | Peripheral clock selection for I2C2. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| PCLK_I2S | Peripheral clock selection for I2S. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| RESERVED | Reserved. |
| PCLK_RIT | Peripheral clock selection for Repetitive Interrupt Timer. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| PCLK_SYSCON | Peripheral clock selection for the System Control block. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |
| PCLK_MC | Peripheral clock selection for the Motor Control PWM. 0 (CCLK_DIV_4): CCLK div 4. PCLK_peripheral = CCLK/4 1 (CCLK): CCLK. PCLK_peripheral = CCLK 2 (CCLK_DIV_2): CCLK div 2. PCLK_peripheral = CCLK/2 3 (CCLK_DIV_8): CCLK div 8. PCLK_peripheral = CCLK/8 |